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// software and tools, and its AMPP partner logic functions, and any output 
// files from any of the foregoing (including device programming or simulation 
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// license agreement, including, without limitation, that your use is for the 
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module Flash_avmm_mux_2to1 
(
    input              clk,           
    input              rst_n,
    output             RSU_FlashBusy,
    //AVMM_Single_Master
    output     reg           slv_csr_addr,          
    output     reg           slv_csr_read,            
    output     reg [31: 0]   slv_csr_writedata,        
    output     reg           slv_csr_write,            
    input          [31: 0]   slv_csr_readdata,      
    output     reg [31: 0]   slv_data_addr,          
    output     reg           slv_data_read,            
    output     reg [31: 0]   slv_data_writedata,        
    output     reg           slv_data_write,            
    input          [31: 0]   slv_data_readdata,           
    input                    slv_data_waitrequest,          
    input                    slv_data_readdatavalid,          
    output     reg [ 6: 0]   slv_data_burstcount,     
    //AVMM_Slave_1
    input              master1_csr_addr,          
    input              master1_csr_read,            
    input      [31: 0] master1_csr_writedata,        
    input              master1_csr_write,            
    output     [31: 0] master1_csr_readdata,      
    input      [31: 0] master1_data_addr,          
    input              master1_data_read,            
    input      [31: 0] master1_data_writedata,        
    input              master1_data_write,            
    output     [31: 0] master1_data_readdata,           
    output             master1_data_waitrequest,          
    output             master1_data_readdatavalid,          
    input      [ 6: 0] master1_data_burstcount,
    //AVMM_Slave_2
    input              master2_csr_addr,          
    input              master2_csr_read,            
    input      [31: 0] master2_csr_writedata,        
    input              master2_csr_write,            
    output     [31: 0] master2_csr_readdata,      
    input      [31: 0] master2_data_addr,          
    input              master2_data_read,            
    input      [31: 0] master2_data_writedata,        
    input              master2_data_write,            
    output     [31: 0] master2_data_readdata,           
    output             master2_data_waitrequest,          
    output             master2_data_readdatavalid,          
    input      [ 6: 0] master2_data_burstcount
);

assign           master1_csr_readdata       =  slv_csr_readdata         ;
assign           master1_data_readdata      =  slv_data_readdata        ;
assign           master1_data_waitrequest   =  slv_data_waitrequest     ;
assign           master1_data_readdatavalid =  slv_data_readdatavalid   ;
assign 			  master2_csr_readdata       =  slv_csr_readdata         ;
assign           master2_data_readdata      =  slv_data_readdata        ;
assign           master2_data_waitrequest   =  slv_data_waitrequest     ;
assign           master2_data_readdatavalid =  slv_data_readdatavalid   ;

assign           RSU_FlashBusy              =   master1_csr_read | master1_csr_write | master1_data_read | master1_data_write;	 

always @ (*) begin
     if( RSU_FlashBusy) begin 
          slv_csr_addr               =  master1_csr_addr ;
          slv_csr_read               =  master1_csr_read ;
          slv_csr_writedata          =  master1_csr_writedata ;
          slv_csr_write              =  master1_csr_write ;
         
          slv_data_addr              =  master1_data_addr;
          slv_data_read              =  master1_data_read;
          slv_data_writedata         =  master1_data_writedata;
          slv_data_write             =  master1_data_write;

          slv_data_burstcount        =  master1_data_burstcount;


     end
     else begin 
          slv_csr_addr               =  master2_csr_addr ;
          slv_csr_read               =  master2_csr_read ;
          slv_csr_writedata          =  master2_csr_writedata ;
          slv_csr_write              =  master2_csr_write ;
      
          slv_data_addr              =  master2_data_addr;
          slv_data_read              =  master2_data_read;
          slv_data_writedata         =  master2_data_writedata;
          slv_data_write             =  master2_data_write;

          slv_data_burstcount        =  master2_data_burstcount;

     end  

end 


endmodule


